Lead FPGA Verification Engineer

Job opening ID
2197

Posting title
Lead FPGA Verification Engineer

Roles and responsibilities
12 month contract position
W2 with full benefits


Job Description:
This position will lead the planning and execution of verification and validation activities for highly complex and unique electronics systems with Laboratory wide impact. Approves all requirements, interfaces, V&V plans, change requests. Develops highly complex and unique test and verification system architectures. Develops advanced and unique modeling approaches. Partners with other engineers, project personnel and management to design and develop highly complex and reusable verification environments.
The verification engineer will:
• Follow the JPL FPGA development procedure
• Participate in peer and developmental reviews
• Perform design analyses and design verification, including test script development
• Provide support to hardware testing and post-delivery integration.


Required Skills:
•Must be a US Citizen or Green Card Holder
•Offer contingent on ability to successfully pass a background check and drug screen
•Bachelor’s degree in Electrical Engineering, Computer Engineering, or related technical discipline with a minimum of 4 years of related experience; a Master’s degree in similar disciplines with typically a minimum of 1 years of related experience; or a PhD in similar disciplines with typically a minimum of 0 years related experience.
•Minimum 4 years of UVM experience required
•Experience with Mentor/Questa preferred
•Proven verification expertise on a project from cradle-to-grave
•Writing verification test plans
•Creating verification environments: block, subsystem, & top-level - Creating test cases
•Running regression
•Gathering and reporting functional and code coverage results
•Working with designers to fix bugs.
•Experience with GIT revision control
•Experience with JIRA bug tracking
•Excellent oral/written communication and presentation skills

Desired Skills:
•Experience with formal verification and SVA.
•Familiarity with standard script languages, such as Python and TCL.


Number of positions
1

Location
Pasadena

State
California