FPGA Verification Engineer

Job opening ID
3153

Posting title
FPGA Verification Engineer

Roles and responsibilities
Must be a US Citizen or Green Card Holder
Estimated duration of 7 months with the potential for extension or conversion.
W2 with full benefits
Customer and contract specific training will be required and provided.
Labor Category: Electrical Engineer IV

Job Description:
The contractor (Raytheon/Paradigm Works) shall provide a full-time FPGA verification engineer over the period starting approximately 12/14/2020 and ending 7/4/2021 to complete the verification of the Psyche MTIF & NVM FPGA design. Tasks will include:
1. Review verification plan/matrix.
2. Developing testbench in UVM/SystemVerilog
3. Developing test cases
4. Debugging failing cases
5. Completing 100% functional and code coverage
6. Participate in peer and developmental reviews
7. Support gate-level simulation

Required Skills:
• Must be a US Citizen or Green Card Holder
• Offer contingent on ability to successfully pass a background check and drug screen
Position requires the following skill set:
1. Experience with complex and large-scale FPGA development.
2. Experience with the latest industry FPGA verification methodologies utilizing UVM and SystemVerilog performed on Mentor Questa sim environment.
3. Experience in all aspects of design verification:
a. Verification planning (Verification plan & Verification matrix)
b. Verification testbench development (block-level & system-level)
c. Test case writing
d. Coverage closure (Functional & code-coverage)
e. Tools:
i. Simulation (Mentor Questa)
ii. Continuous integration (Bamboo)
iii. Configuration management (git)
iv. Bug-tracking (JIRA)
v. Formal verification ()
4. Excellent oral/written communication and presentation skills.
5. Ability to work effectively in a team.

Desired Skills:
Experienced debugging/identifying RTL issues


Number of positions
1

Location
Pasadena

State
California