Verification Engineer

Job opening ID

1202

Posting title

Verification Engineer

Roles and responsibilities

Must be a US Citizen. 
W2 w/Full Benefits
12-18 month contract position with potential for extension
Must be able to pass background and drug test

Job description:
Verification Engineer you will be responsible for planning and executing the verification for a digital design implemented on an FPGA.

Required Skills:
• Minimum 4 years of UVM experience required.
- Experience with Mentor/Questa preferred
• Proven verification expertise on a project from cradle-to-grave
- Writing verification test plans
- Creating verification environments: block, subsystem, & top-level
- Creating test cases
- Running regression
- Gathering and reporting functional and code coverage results
- Working with designers to fix bugs.
• Experience with GIT revision control
• Experience with JIRA bug tracking
• Excellent oral/written communication and presentation skills.

This position requires a Bachelor’s degree in Electrical Engineering, Computer Engineering, or related technical discipline with a minimum of 9 years of related experience; a Master’s degree in similar disciplines with typically a minimum of 7 years of related experience; or a PhD in similar disciplines with typically a minimum of 5 years related experience.

Desired Skills:
• Experience with formal verification and SVA.
• Familiarity with standard script languages, such as Python and TCL.

Number of positions

1

Location

Pasadena

State

California